If 7nm is the physical limit of the manufacturing process, then what is the concept of 1nm?
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Moore's Law, which has been applicable for more than 20 years, has gradually shown signs of failure in recent years. From the perspective of chip manufacturing, 7nm is the physical limit of silicon chips. However, according to foreign media reports, a team at Lawrence Berkeley National Laboratory broke the physical limit and used carbon nanotube composite materials to reduce the current most advanced transistor process from 14nm to 1nm. So, why is 7nm the physical limit of silicon chips, and what is the carbon nanotube composite material? Faced with the technological breakthrough of the United States, what should China do? What is the concept of XX nm manufacturing process? The manufacturing process of chips is often expressed as 90nm, 65nm, 40nm, 28nm, 22nm, and 14nm. For example, Intel's latest six-generation Core series CPU uses Intel's own 14nm manufacturing process. Today's CPUs integrate transistors in billions of units. This transistor consists of a source, a drain, and a gate between them. The current flows from the source to the drain, and the gate plays a role in controlling the on and off of the current. The so-called XX nm actually refers to the width of the gate of the complementary oxide metal semiconductor field effect transistor formed on the CPU, also known as the gate length. The shorter the gate length, the more transistors can be integrated on the same size silicon wafer - Intel once claimed that when the gate length is reduced from 130nm to 90nm, the area occupied by the transistor will be reduced by half; when the integration of chip transistors is the same, the more advanced manufacturing process is used, the smaller the chip area and power consumption, and the lower the cost. The gate length can be divided into the photolithography gate length and the actual gate length, of which the photolithography gate length is determined by the photolithography technology. Due to the diffraction phenomenon of light in photolithography and the steps of ion implantation, etching, plasma washing, heat treatment, etc. in chip manufacturing, the photolithography gate length and the actual gate length will be inconsistent. In addition, under the same process technology, the actual gate length will also be different. For example, although Samsung has also launched a chip with a 14nm process technology, the actual gate length of its chip is still a certain distance from the actual gate length of Intel's 14nm process chip. Why is 7nm the physical limit? Shortening the length of the transistor gate can enable the CPU to integrate more transistors or effectively reduce the area and power consumption of transistors, and cut the silicon wafer cost of the CPU. For this reason, CPU manufacturers spare no effort to reduce the gate width of transistors to increase the number of transistors integrated per unit area. However, this approach will also shorten the distance that electrons move, which can easily lead to the spontaneous movement of electrons inside the transistor from the negative electrode to the positive electrode through the silicon bottom plate of the transistor channel, that is, leakage. Moreover, as the number of transistors in the chip increases, the silicon dioxide insulating layer, which was originally only a few atomic layers thick, will become thinner, resulting in more electrons leaking, and the subsequent leakage current will increase the additional power consumption of the chip. In order to solve the leakage problem, companies such as Intel and IBM can be said to have shown their magical powers. For example, Intel has integrated high-dielectric films and metal gate integrated circuits in its manufacturing process to solve the leakage problem; IBM has developed SOI technology - burying a layer of strong dielectric film in the source and drain to solve the leakage problem; in addition, there is fin field-effect transistor technology (FinFET) - by increasing the surface area of the insulating layer to increase the capacitance value, reduce the leakage current to prevent the occurrence of electron transitions... The above approach can effectively solve the leakage problem to a certain extent when the gate length is greater than 7nm. However, based on the existing chip materials, once the gate length of the transistor is less than 7nm, the electrons in the transistor will easily produce a tunneling effect, which brings great challenges to the manufacture of chips. In response to this problem, finding new materials to replace silicon to make transistors below 7nm is an effective solution. 1nm process transistors are still in the laboratory stage Carbon nanotubes are related to graphene, which has been very popular in recent years. Zero-dimensional fullerene, one-dimensional carbon nanotubes, and two-dimensional graphene all belong to the family of carbon nanomaterials, and they can be transformed in form after meeting certain conditions. Carbon nanotubes are a one-dimensional material with a special structure. Its radial size can reach the nanometer level, and its axial size is micrometer level. Both ends of the tube are generally sealed, so it has great strength. At the same time, the huge aspect ratio is expected to make it into carbon fiber with excellent toughness. Carbon nanotubes and graphene have similar properties in electricity and mechanics, and have good electrical conductivity, mechanical properties and thermal conductivity, which makes carbon nanotube composites have good application prospects in supercapacitors, solar cells, displays, biological detection, fuel cells, etc. In addition, carbon nanotube composite materials doped with some modifiers have also attracted widespread attention, such as adding CdTe quantum dots to graphene/carbon nanotube composite electrodes to make photoelectric switches and doping metal particles to make field emission devices. The Lawrence Berkeley National Laboratory reported by foreign media this time has reduced the most advanced transistor process from 14nm to 1nm, and its transistors are made of carbon nanotubes doped with molybdenum disulfide. However, this technological achievement is only at the stage of laboratory technology breakthrough, and there is currently no commercial mass production capability. As for whether this technology will become a mainstream commercial technology in the future, it remains to be tested by time. Technological progress does not necessarily bring commercial benefits. In the past few decades, due to the fact that Moore's Law is really working, China's semiconductor manufacturing technology has always been pulled a distance away from foreign countries in the process of catching up with the West. In recent years, the progress of chip manufacturing technology has slowed down, and the objective phenomenon of Moore's Law failing is a big benefit for China's semiconductor industry to catch up with the West. The failure of Moore's Law is due to both technical factors on the one hand - the difficulty of developing advanced photolithography equipment, etching machines and advanced chip manufacturing technology, and the high capital requirements... On the other hand, there are also commercial factors. Before the manufacturing process reached 28nm, every advancement in the manufacturing process could enable chip manufacturers to make huge profits. However, after the manufacturing process reached 14/16nm, technological progress will increase the cost of chips - when Intel first developed the 14nm manufacturing process, it was reported that its mask cost was 300 million US dollars. Of course, with the passage of time and TSMC and Samsung mastering the 14/16nm process, the current price should not be so expensive, but Intel is developing the 10nm process, according to Intel's official estimate, the mask cost will be at least 1 billion US dollars. The reason why new manufacturing processes are expensive is that, on the one hand, they are expensive because of the high R&D costs and low yield of new processes, and on the other hand, because the prices of equipment such as lithography machines and etching machines are extremely expensive. Therefore, even if the advanced manufacturing process is technically mature, the excessively high mask costs will make customers think twice before choosing to adopt the most advanced manufacturing process. For example, if the output of 10nm manufacturing process chips is less than 10 million pieces, the mask cost allocated to each chip alone is as high as $100. According to the internationally common pricing strategy of low-profit chip design companies, the 8:20 pricing method - that is, when the hardware cost is 8, the price is 20. Don't think this price is high, it is actually very low. Intel's general pricing strategy is 8:35, and AMD has historically reached 8:50... Even if the chip cost and packaging and testing costs are not counted, the price of this 10nm CPU will not be less than $250. At the same time, the relatively small number of customers will make it difficult to share costs with huge output, and ultimately slow down the development and commercial application of advanced manufacturing processes. It is for this reason that the 28nm manufacturing process is considered by some industry insiders to be very dynamic and will continue to be used for several years. China should solve practical problems down to earth. As for the fact that the Lawrence Berkeley National Laboratory has reduced the most advanced transistor process from 14nm to 1nm, Chinese people do not need to take it too seriously, because this is just a technological breakthrough in the laboratory. Even if we take a step back and say that the technology is mature and can be commercialized, its difficulty in commercialization is far greater than the 10nm manufacturing process that Intel is developing. Its cost will be extremely high, which will make the price of chips produced using this technology high, which will in turn lead to fewer customers choosing this technology, and then a vicious cycle... Considering commercial factors, most IC design companies will probably still choose relatively mature, or relatively "old" manufacturing processes. For the current Chinese semiconductor industry, instead of spending huge manpower, material and financial resources to explore and break through the physical limit of 7nm, it is better to use limited manpower, material and financial resources to improve the IP library of the 28nm process technology and realize the commercial mass production of the 14nm manufacturing process. After all, for the field of national defense and security, the existing manufacturing process is completely sufficient (many military chips in the United States are still 65nm). For commercial chips, many chips do not have high requirements for the process. Industrial control chips, automotive electronics, radio frequency, etc. are all using processes that seem old to some hardware enthusiasts. For the CPU and GPU of PCs, mobile phones, and tablets, the 14nm/16nm manufacturing process can already balance the performance and power consumption requirements very well. The author believes that compared to spending a lot of resources to develop new materials to break through the physical limit of 7nm, it is better to solve practical problems down to earth. As a winner of Toutiao's Qingyun Plan and Baijiahao's Bai+ Plan, the 2019 Baidu Digital Author of the Year, the Baijiahao's Most Popular Author in the Technology Field, the 2019 Sogou Technology and Culture Author, and the 2021 Baijiahao Quarterly Influential Creator, he has won many awards, including the 2013 Sohu Best Industry Media Person, the 2015 China New Media Entrepreneurship Competition Beijing Third Place, the 2015 Guangmang Experience Award, the 2015 China New Media Entrepreneurship Competition Finals Third Place, and the 2018 Baidu Dynamic Annual Powerful Celebrity. |
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